Abstract—Miniaturization enhancement in the scaling technology has

Abstract—Miniaturization has been a constant
challenge to meet the demands of high performance, high density, lower power, and
lower voltage complex devices. Miniaturization is the main drive force for the
migration from micro electronic device structures to nano electronic device
structures. Planar CMOS scaling has been delivering better performance &
low power devices at each cutting edge of the technology node for more than three
decades. Now, CMOS scaling is facing crucial limitations and some show stoppers
are affecting bulk CMOS scaling. So, Semiconductor industry is witnessing the
phase-out of Planar CMOS with the introduction of new device architecture like 3D
FinFET technology for extending the Moore’s Law for Nanoscale technologies. This
paper discusses the evolution of Planar CMOS technology, CMOS Scaling
challenges, Planar CMOS Optimization technologies & the next generation
Nano architectures in order to extend the scaling beyond planar CMOS. FinFET is
emerging technology beyond 22nm. This paper studies FinFET architecture, advantages
and manufacturing challenges associated with it. It also throws light on future
technologies like Carbon nanotube, Silicon Nanowire FET and Tunneling FET etc.


Index Terms—FinFET,
CMOS Scaling, FD-SOI, HKMG, Carbon nanotube, Nanowire FET, Tunneling FET.

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I. Introduction

device industry has marched at the pace of Moore’s Law. The number of
transistors doubles approximately every two years as a result of continuous scaling
of transistors, which has, been the distinct feature of the semiconductor manufacturing
Industry. Each newer technology generation produces more functionality, denser
& faster transistors that can switch fast compared to the previous
generation technology 1.

The size of the transistors is decreasing continuously with the decrease
in the thickness of the silicon dioxide gate dielectric to increase the gate
capacitance and thereby increasing the drive current, which ultimately provides
better device performance 14. The CMOS scaling of the devices is facing challenges
due to shrinking geometries, lower supply voltage, and higher frequencies, which
have negative impact on the device by increasing short channel effect due to
which leakage (gate leakage and sub-threshold leakage) in the device is increasing
constantly. The enhancement in the scaling technology has increased the need of
low power based circuits 14. In nanometer devices, CMOS based circuit are not
used due to problem in its fundamental material, short channel effect and high
leakage 14. New technologies are needed for handling the various effects of
MOSFET technology. As the planar MOSFETs shows a significant SCE (Short Channel
Effect) and hence the designers are concentrating on FinFETs, which have
negligible SCE for the same channel length.

FinFETs have attracted increasing attention
over the past decade because of the degrading short-channel behaviour of planar
MOSFETs. In the planar MOSFET channel is horizontal, the FinFET channel (also
known as the fin) is vertical. With multiple fins and smaller fin heights leads
to more flexible and width of the channel can be increased, which in turn leads
to more silicon area.